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general description the max1332/max1333 2-channel, serial-output, 12-bit, analog-to-digital converters (adcs) feature two true-differential analog inputs and offer outstanding noise immunity and dynamic performance. both devices easily interface with spi/qspi/microwire and standard digital signal processors (dsps). the max1332 operates from a single supply of +4.75v to +5.25v with sampling rates up to 3msps. the max1333 operates from a single supply of +2.7v to +3.6v with sampling rates up to 2msps. these devices feature a partial power-down mode and a full power- down mode that reduce the supply current to 3.3ma and 0.2?, respectively. also featured is a separate power supply input (dv dd ) that allows direct interfacing to +2.7v to +3.6v digital logic. the fast conversion speed, low power dissipation, excellent ac perfor- mance, and dc accuracy (?.6 lsb inl) make the max1332/max1333 ideal for industrial process control, motor control, and base-station applications. the max1332/max1333 are available in a space-sav- ing (3mm x 3mm), 16-pin, tqfn package and operate over the extended (-40? to +85?) temperature range. applications data acquisition bill validation motor control base stations high-speed modems optical sensors industrial process control features ? 3msps sampling rate (+5v, max1332) ? 2msps sampling rate (+3v, max1333) ? separate logic supply: +2.7v to +3.6v ? two true-differential analog input channels ? bipolar/unipolar selection input ? only 38mw (typ) power consumption ? only 2? (max) shutdown current ? high-speed, spi-compatible, 3-wire serial interface ? 2mhz full-linear bandwidth ? 71.4db sinad and -93db thd at 525khz input frequency ? no pipeline delays ? space-saving (3mm x 3mm), 16-pin, tqfn package max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs ________________________________________________________________ maxim integrated products 1 ordering information ain1p dout sclk cnvst ain1n ref differential inputs +4.75v to +5.25v +2.7v to +3.6v c/dsp chsel + - av dd dv dd agnd agnd dgnd bip/uni shdn 0.1 f 0.1 f 1 f 1 f 0.1 f 1 f ain0p ain0n ref input voltage + - max1332 typical operating circuit 19-3712; rev 0; 5/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max1332 ete* -40? to +85? 16 tqfn-ep** (3mm x 3mm) max1333 ete -40? to +85? 16 tqfn-ep** (3mm x 3mm) spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. *future product?ontact factory for availability. **ep = exposed paddle. selector guide and pin configuration appear at end of data sheet.
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd (max1332) ......................................-0.3v to +6v av dd to agnd (max1333) ......................................-0.3v to +4v dv dd to dgnd.........................................................-0.3v to +4v agnd to dgnd.....................................................-0.3v to +0.3v sclk, cnvst, shdn , chsel, bip/ uni , dout to dgnd ...................................-0.3v to (dv dd + 0.3v) ain0p, ain0n, ain1p, ain1n, ref to agnd...................................................-0.3v to (av dd + 0.3v) maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70?) 16-pin tqfn (derate 17.5mw/? above +70?) ....1398.6mw operating temperature range max133_ete ...................................................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (max1332) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +3.6v, f sclk = 48mhz, v ref = 4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dc accuracy (bip/ uni = dgnd) (note 1) resolution n 12 bits integral nonlinearity inl ?.6 ?.0 lsb differential nonlinearity dnl ?.6 ?.0 lsb offset error ?.9 ?.0 lsb gain error ?.6 ?.0 lsb offset-error temperature coefficient ?.2 ppm/? gain-error temperature coefficient ?.1 ppm/? dynamic specifications (a in = -0.2dbfs, f in = 525khz, bip/ uni = dv dd , unless otherwise noted) (note 1) signal-to-noise ratio snr 70 71.5 db signal-to-noise plus distortion sinad 70 71.4 db total harmonic distortion thd -93 -84 dbc spurious-free dynamic range sfdr 84 93 dbc channel-to-channel isolation 76 db full-linear bandwidth sinad > 68db 2 mhz full-power bandwidth 6 mhz small-signal bandwidth 6 mhz conversion rate minimum conversion time t conv figure 5 271 ns maximum throughput rate 3 msps minimum track-and-hold acquisition time t acq figure 5 52 ns
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs _______________________________________________________________________________________ 3 electrical characteristics (max1332) (continued) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +3.6v, f sclk = 48mhz, v ref = 4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units aperture delay t ad figure 21 <10 ns aperture jitter t aj figure 21 <10 ps differential analog inputs (ain0p, ain0n, ain1p, ain1n) bip/ uni = dgnd 0 v ref v differential input voltage range (v ain_p - v ain_n ) v in bip/ uni = dv dd -v ref / 2 +v ref / 2 absolute input voltage range agnd - 50mv av dd + 50mv v dc leakage current i lkg ? ? input capacitance c in 14 pf reference input (ref) ref input voltage range v ref 1.0 av dd + 50mv v ref input capacitance c ref 14 pf ref dc leakage current i ref ?0 ? digital inputs (sclk, cnvst, shdn , chsel, bip/ uni ) input-voltage low v il 0.3 x dv dd v input-voltage high v ih 0.7 x dv dd v input hysteresis 100 mv input leakage current i ilkg ?.2 ? ? input capacitance c in 15 pf digital output (dout) output-voltage low v ol i sink = 5ma 0.4 v output-voltage high v oh i source = 1ma dv dd - 0.5 v tri-state leakage current i lkgt between conversions, cnvst = dv dd ? ? tri-state output capacitance c out between conversions, cnvst = dv dd 15 pf power requirements analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.7 3.6 v normal mode; average current (f sample = 3mhz, f sclk = 48mhz) 11 12 partial power-down mode 3.5 6 ma analog supply current i avdd full power-down mode 0.1 2 a
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 4 _______________________________________________________________________________________ electrical characteristics (max1332) (continued) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +3.6v, f sclk = 48mhz, v ref = 4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units average current (f sample = 3mhz, f sclk = 48mhz, zero-scale input) 4.5 7 ma power-down (f sclk = 48mhz), cnvst = dv dd 15 30 digital supply current i dvdd static; all digital inputs are connected to dv dd or dgnd 0.2 2 ? power-supply rejection psr av dd = 4.75v to 5.25v, full-scale input ? mv timing characteristics (max1332) (figure 4) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units sclk clock period t cp 20.8 ns sclk pulse width t spw 6ns cnvst rise to dout disable t crdd 15 ns cnvst fall to dout enable t cfde 15 ns chsel to cnvst fall setup t chcf 40 ns bip/ uni to cnvst fall setup t bucf 40 ns cnvst fall to chsel hold t cfch 0ns sclk fall to bip/ uni hold t cfbu 0ns dout remains valid after sclk t dhold c load = 0pf (note 2) 1 2 ns sclk rise to dout transition t dot c load = 30pf 6 ns cnvst to sclk rise t setup 6ns sclk rise to cnvst t hold 0ns cnvst pulse width t csw 6ns minimum recovery time (full power-down) t fpd from cnvst fall or shdn rise 4 s minimum recovery time (partial power-down) t ppd from cnvst fall 500 ns note 1: tested with av dd = 4.75v and dv dd = +2.7v. note 2: guaranteed by design, not production tested.
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs _______________________________________________________________________________________ 5 electrical characteristics (max1333) (av dd = +2.7v to +3.6v, dv dd = +2.7v to av dd , f sclk = 32mhz, v ref = 2.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dc accuracy (note 3) (bip/ uni = dgnd) resolution n 12 bits relative accuracy inl ?.6 ?.0 lsb differential nonlinearity dnl ?.6 ?.0 lsb offset error ?.9 ?.0 lsb gain error ?.6 ?.0 lsb offset-error temperature coefficient ?.1 ppm/? gain-error temperature coefficient ?.2 ppm/? dynamic specifications (a in = -0.2dbfs, f in = 525khz, bip/ uni = dv dd , unless otherwise noted) (note 3) signal-to-noise ratio snr 70 71.5 db signal-to-noise plus distortion sinad 70 71.4 db total harmonic distortion thd -93 -86.5 dbc spurious-free dynamic range sfdr 83.5 93 dbc channel-to-channel isolation 76 db full-linear bandwidth sinad > 68db 1.7 mhz full-power bandwidth 5.5 mhz small-signal bandwidth 5 mhz conversion rate minimum conversion time t conv figure 5 406 ns maximum throughput rate 2.0 msps minimum track-and-hold acquisition time t acq figure 5 78 ns aperture delay t ad figure 21 <10 ns aperture jitter t aj figure 21 <10 ps differential analog inputs (ain0p, ain0n, ain1p, ain1n) bip/ uni = dgnd 0 v ref differential input voltage range (v ain_p - v ain_n ) v in bip/ uni = dv dd -v ref / 2 +v ref / 2 v absolute input voltage range agnd - 50mv av dd + 50mv v dc leakage current i lkg ? ?
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 6 _______________________________________________________________________________________ electrical characteristics (max1333) (continued) (av dd = +2.7v to +3.6v, dv dd = +2.7v to av dd , f sclk = 32mhz, v ref = 2.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units input capacitance c in 14 pf reference input (ref) ref input voltage v ref 1.0 av dd + 50mv v ref input capacitance c ref 14 pf ref dc leakage current i ref ?0 ? digital inputs (sclk, cnvst, shdn , chsel, bip/ uni ) input-voltage low v il 0.3 x dv dd v input-voltage high v ih 0.7 x dv dd v input hysteresis 100 mv input leakage current i ilkg ?.2 ? ? input capacitance c in 15 pf digital output (dout) output-voltage low v ol i sink = 5ma 0.4 v output-voltage high v oh i source = 1ma dv dd - 0.5 v tri-state leakage current i lkgt between conversions, cnvst = dv dd ? ? tri-state output capacitance c out between conversions, cnvst = dv dd 15 pf power requirements analog supply voltage av dd 2.7 3.6 v digital supply voltage dv dd 2.7 av dd v normal mode; average current (f sample = 2mhz, f sclk = 32mhz) 9.5 11.5 partial power-down mode 3.3 4 ma analog supply current i avdd full power-down mode 0.1 2 a average current (f sample = 2mhz, f sclk = 32mhz, zero-scale input) 3 5.4 ma power-down (f sclk = 32mhz, cnvst = dv dd ) 10 20 digital supply current i dvdd static; all digital inputs are connected to dv dd or dgnd 0.2 2 ? positive supply rejection psr av dd = 2.7v to 3.6v, full-scale input ? mv
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs _______________________________________________________________________________________ 7 timing characteristics (max1333) (figure 4) (av dd = +2.7v to +3.6v, dv dd = +2.7v to av dd , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units sclk clock period t cp 31.2 ns sclk pulse width t cpw 10 ns cnvst rise to dout disable t crdd 15 ns cnvst fall to dout enable t cfde 15 ns chsel to cnvst fall setup t chcf 50 ns bip/ uni to cnvst fall setup t bucf 50 ns cnvst fall to chsel hold t cfch 0ns sclk fall to bip/ uni hold t cfbu 0ns dout remains valid after sclk t dhold c load = 0pf (note 4) 1 2 ns sclk rise to dout transition t dot c load = 30pf 6 ns cnvst to sclk rise t setup 6ns sclk rise to cnvst t hold 0ns cnvst pulse width t csw 6ns minimum recovery time (full power-down) t fpd from cnvst fall or shdn rise 4 s minimum recovery time (partial power-down) t ppd from cnvst fall 500 ns note 3: tested with av dd = dv dd = +2.7v. note 4: guaranteed by design, not production tested. dgnd 6k ? 30pf dout a) high impedance to v oh , v ol to v oh , and v oh to high impedance 6k ? 30pf dout dgnd dv dd b) high impedance to v ol , v oh to v ol , and v ol to high impedance figure 1. load circuits for enable/disable times
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 8 _______________________________________________________________________________________ typical operating characteristics (av dd = +5v, dv dd = +3v, v ref = 4.096v, f sclk = 64mhz. t a = +25?, unless otherwise noted.) av dd supply current vs. temperature max1332 toc04 temperature ( c) i avdd (ma) 60 35 10 -15 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0 10.0 -40 85 zero-scale input f sclk = 64mhz offset error vs. av dd max1332 toc01 av dd (v) offset error (lsb) 5.15 4.85 5.05 4.95 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 4.75 5.25 dv dd = +3v f sclk = 64mhz gain error vs. av dd max1332 toc02 av dd (v) gain error (lsb) 5.15 4.85 5.05 4.95 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 4.75 5.25 dv dd = +3v f sclk = 64mhz gain error vs. av dd max1332 toc03 av dd (v) gain error (lsb) 5.15 4.85 5.05 4.95 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 4.75 5.25 dv dd = +3v f sclk = 64mhz av dd supply current vs. f sclk max1332 toc05 f sclk (mhz) i avdd (ma) 56 48 8 16 24 32 40 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 8.0 064 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 8.0 max1332 toc06 av dd (v) 5.15 4.85 5.05 4.95 4.75 5.25 dv dd = +3v zero-scale input f sclk = 64mhz av dd supply current vs. av dd i avdd (ma) max1332
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs _______________________________________________________________________________________ 9 total supply current vs. throughput rate max1332 toc10 f cnvst (mhz) i avdd + i dvdd (ma) 1 0.1 0.01 1 10 100 0.1 0.001 10 full power-down partial power-down no power-down 2.5 3.0 3.5 4.0 5.0 4.5 5.5 6.0 2.0 dv dd supply current vs. temperature max1332 toc07 temperature ( c) i dvdd (ma) 60 35 10 -15 -40 85 zero-scale input f sclk = 64mhz 1 2 3 4 5 6 0 dv dd supply current vs. f sclk max1332 toc08 f sclk (mhz) i dvdd (ma) 56 48 8 16243240 064 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 3 4 5 6 7 8 2 2.7 3.6 max1332 toc09 dv dd (v) av dd = +5v zero-scale input f sclk = 64mhz dv dd supply current vs. dv dd i dvdd (ma) typical operating characteristics (continued) (av dd = +5v, dv dd = +3v, v ref = 4.096v, f sclk = 64mhz. t a = +25?, unless otherwise noted.) max1332
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 10 ______________________________________________________________________________________ -1.0 -0.6 -0.8 -0.2 -0.4 0.2 0 0.4 0.8 0.6 1.0 0 1024 1536 512 2048 2560 3072 3584 4096 integral nonlinearity vs. output code max1333 toc01 output code inl (lsb) f sclk = 32mhz -1.0 -0.6 -0.8 -0.2 -0.4 0.2 0 0.4 0.8 0.6 1.0 0 1024 1536 512 2048 2560 3072 3584 4096 differential nonlinearity vs. output code max1333 toc02 output code dnl (lsb) f sclk = 32mhz -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -40 -15 10 35 60 85 offset error vs. temperature max1333 toc03 temperature ( c) offset error (lsb) av dd = +3v 3.5 3.4 3.2 3.3 2.9 3.0 3.1 2.8 -3 -2 -1 0 1 2 3 4 -4 2.7 3.6 offset error vs. av dd max1333 toc04 offset error (lsb) dv dd = av dd av dd (v) -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -40 -15 10 35 60 85 gain error vs. temperature max1333 toc05 temperature ( c) gain error (lsb) av dd = +3v 3.5 3.4 2.8 2.9 3.0 3.2 3.1 3.3 2.7 3.6 gain error vs. av dd max1333 toc06 av dd (v) gain error (lsb) -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 dv dd = av dd av dd supply current vs. temperature max1333 toc07 temperature ( c) i avdd (ma) 60 35 10 -15 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 8.0 -40 85 zero-scale input f sclk = 40mhz av dd supply current vs. f sclk max1333 toc08 f sclk (mhz) i avdd (ma) 35 30 5 10 15 20 25 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 8.0 040 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 8.0 max1333 toc09 av dd (v) av dd = dv dd zero-scale input f sclk = 40mhz av dd supply current vs. av dd i avdd (ma) 3.5 3.4 2.8 2.9 3.0 3.2 3.1 3.3 2.7 3.6 typical operating characteristics (continued) (av dd = +3v, dv dd = +3v, v ref = 2.5v, f sclk = 40mhz. t a = +25?, unless otherwise noted.) max1333
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs ______________________________________________________________________________________ 11 typical operating characteristics (continued) (av dd = +3v, dv dd = +3v, v ref = 2.5v, f sclk = 40mhz. t a = +25?, unless otherwise noted.) dv dd supply current vs. temperature max1333 toc10 temperature ( c) i dvdd (ma) 60 35 10 -15 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 1.00 -40 85 zero-scale input f sclk = 40mhz 35 30 5 10 15 20 25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 040 dv dd supply current vs. f sclk max1333 toc11 f sclk (mhz) i dvdd (ma) 2.95 2.90 2.75 2.80 2.85 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 2.70 3.00 max1333 toc12 dv dd (v) av dd = +3v zero-scale input f sclk = 40mhz dv dd supply current vs. dv dd i dvdd (ma) sinad vs. input frequency max1333 toc13 input frequency (khz) sinad (db) 1600 1200 800 400 64 66 68 70 72 62 0 2000 f sclk = 32mhz sfdr vs. input frequency max1333 toc14 input frequency (khz) sfdr (dbc) 1600 1200 800 400 76 82 88 94 100 70 0 2000 f sclk = 32mhz thd vs. input frequency max1333 toc15 input frequency (khz) thd (dbc) 1600 1200 800 400 -94 -88 -82 -76 -70 -100 0 2000 f sclk = 32mhz output amplitude vs. input frequency max1333 toc16 input frequency (mhz) output amplitude (dbfs) 7 6 5 4 3 2 1 -5 -4 -3 -2 -1 0 -6 08 f sclk = 32mhz ain = -0.1dbfs max1333 total supply current vs. throughput rate max1333 toc17 f cnvst (mhz) i avdd + i dvdd (ma) 1 0.1 0.01 1 10 100 0.1 0.001 10 full power-down partial power-down no power-down
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 12 ______________________________________________________________________________________ pin description pin name function 1 ain0p positive analog-input channel 0 2 ain0n negative analog-input channel 0 3 ain1p positive analog-input channel 1 4 ain1n negative analog-input channel 1 5 ref external reference voltage input. v ref = 1v to (av dd + 50mv). bypass ref to agnd with a 0.1? and a 1?. 6 shdn shutdown input. pull shdn low to enter full power-down mode. drive shdn high to resume normal operation regardless of previous software entered into power-down mode. 7 bip/ uni analog-input-mode select. drive bip/ uni high to select bipolar-input mode. pull bip/ uni low to select unipolar-input mode. 8 agnd analog ground. connect all agnds and ep to the same potential. 9 chsel channel-select input. drive chsel high to select channel 1. pull chsel low to select channel 0. 10 cnvst conversion-start input. the first rising edge of cnvst powers up the max1332/max1333 and begins acquiring the analog input. a falling edge samples the analog input and starts a conversion. cnvst also controls the power-down mode of the device (see the partial power-down (ppd) and full power- down (fpd) mode section). 11 sclk serial-clock input. clocks data out of the serial interface. sclk also sets the conversion speed. 12 dout serial-data output. data is clocked out on the rising edge of sclk (see the starting a conversion section). 13 dv dd positive-digital-supply input. dv dd is the positive supply input for the digital section of the max1332/max1333. connect dv dd to a 2.7v to 3.6v power supply. bypass dv dd to dgnd with a 0.1? capacitor in parallel with a 1? capacitor. place the bypass capacitors as close to the device as possible. 14 dgnd digital ground. ensure that the potential difference between agnd and dgnd is less than ?.3v. 15 av dd positive-analog-supply input. av dd is the positive supply input for the analog section of the max1332/max1333. connect av dd to a 4.75v to 5.25v power supply for the max1332. connect av dd to a 2.7v to 3.6v power supply for the max1333. bypass av dd to agnd with a 0.1? capacitor in parallel with a 1? capacitor. place the bypass capacitors as close to the device as possible. 16 agnd analog ground. connect all agnds and ep to the same potential. ?pe xp osed p ad d l e. inter nal l y connected to agn d . c onnect the exp osed p ad d l e to the anal og g r ound p l ane.
detailed description the max1332/max1333 use an input track and hold (t/h) circuit along with a successive-approximation register (sar) to convert a differential analog input sig- nal to a digital 12-bit output. the serial interface requires only three digital lines (sclk, cnvst, and dout) and provides easy interfacing to microcon- trollers (?s) and dsps. figure 2 shows the simplified block diagram for the max1332/max1333. power supplies the max1332/max1333 accept two power supplies that allow the digital noise to be isolated from sensitive analog circuitry. for both the max1332 and max1333, the digital power-supply input accepts a supply voltage of +2.7v to +3.6v. however, the supply voltage range for the analog power supply is different for each device. the max1332 accepts a +4.75v to +5.25v analog power supply, and the max1333 accepts a +2.7v to +3.6v analog power supply. see the layout, grounding, and bypassing section for information on how to isolate digital noise from the analog power input. the max1332/max1333s?analog power supply con- sists of one av dd input, two agnd inputs, and the exposed paddle (ep). the digital power input consists of one dv dd input and one dgnd input. ensure that the potential on both agnd inputs is the same. furthermore, ensure that the potential between agnd and dgnd is limited to ?.3v. ideally there should be no potential difference between agnd and dgnd. there are no power sequencing issues between av dd and dv dd . the analog and digital power supplies are insensitive to power-up sequencing. true-differential analog input t/h the equivalent input circuit of figure 3 shows the max1332/max1333s?input architecture, which is com- posed of a t/h, a comparator, and a switched-capaci- tor dac. on power-up, the max1332/max1333 enter full power-down mode. drive cnvst high to exit full power-down mode and to start acquiring the input. the positive input capacitor is connected to ain_p and the negative input capacitor is connected to ain_n. the t/h enters its hold mode on the falling edge of cnvst and the adc starts converting the sampled difference between the analog inputs. once a conversion has been initiated, the t/h enters acquisition mode for the next conversion on the 13th falling edge of sclk after cnvst has been transitioned from high to low. the time required for the t/h to acquire an input signal is determined by how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens. the acquisition time, t acq , is the minimum time needed for the signal to be acquired. it is calculated by the following equation: t acq k x (r source + r in ) x c in where: the constant k is the number of rc time constants required so that the voltage on the internal sampling capacitor reaches n-bit accuracy, i.e., so that the dif- ference between the input voltage and the sampling capacitor voltage is equal to 0.5 lsb. n = 12 for the max1332/max1333. r in = 250 ? is the equivalent differential analog input resistance, c in = 14pf is the equivalent differential ana- log input capacitance, and r source is the source impedance of the input signal. note that t acq is never less than 52? for the max1332 and 78? for the max1333, and any source impedance below 160 ? does not significantly affect the adc? ac performance. input bandwidth the adc? input-tracking circuitry has a 5mhz small- signal bandwidth, making it possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-fre- quency signals being aliased into the frequency band k n = 922 ln ( ) max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs ______________________________________________________________________________________ 13 dout dv dd ref 12-bit sar adc cnvst shdn sclk chsel bip/uni dgnd control logic and timing av dd agnd ain0p ain0n input mux and t/h ain1p ain1n max1332 max1333 output buffer figure 2. simplified functional diagram
max1332/max1333 of interest, lowpass or bandpass filtering is recom- mended to limit the bandwidth of the input signal. input buffer to improve the input signal bandwidth under ac condi- tions, drive the input with a wideband buffer (>50mhz) that can drive the adc? input capacitance (14pf) and settle quickly. most applications require an input buffer to achieve 12-bit accuracy. although slew rate and bandwidth are important, the most critical input buffer specification is settling time. the sampling requires an acquisition time of 52? for the max1332 and 78? for the max1333. at the beginning of the acquisition, the adc internal sampling capacitors connect to the ana- log inputs, causing some disturbance. ensure the amplifier is capable of settling to at least 12-bit accura- cy during this interval. use a low-noise, low-distortion, wideband amplifier that settles quickly and is stable with the adc? 14pf input capacitance. see the maxim website (www.maxim-ic.com) for appli- cation notes on how to choose the optimum buffer amplifier for an adc application. the max4430 is one of the devices that is ideal for this application. differential analog input range and protection the max1332/max1333 produce a digital output that corresponds to the differential analog input voltage as long as the differential analog inputs are within the specified range. when operating in unipolar mode (bip/ uni = 0), the usable differential analog input range is from 0 to v ref . when operating in bipolar mode (bip/ uni = 1), the differential analog input range is from -v ref /2 to +v ref /2. in both unipolar and bipolar 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 14 ______________________________________________________________________________________ control logic capacitive dac ain_p ain_n agnd av dd c in+ r in+ c in- r in- comp figure 3b. equivalent input circuit (hold/conversion mode) control logic capacitive dac ain_p ain_n agnd av dd c in+ r in+ c in- r in- comp figure 3a. equivalent input circuit (acquisition mode)
modes, the input common-mode voltage can vary as long as the voltage at any single analog input (v ain_p , v ain_n ) remains within 50mv of the analog power sup- ply rails (av dd , agnd). as shown in figure 3, internal protection diodes confine the analog input voltage within the region of the analog power-supply rails (av dd , agnd) and allow the analog input voltage to swing from agnd - 0.3v to av dd + 0.3v without damage. input voltages beyond agnd - 0.3v and av dd + 0.3v forward bias the internal protection diodes. in this situation, limit the forward diode current to 50ma to avoid damaging the max1332/max1333. serial digital interface timing and control conversion-start and data-read operations are con- trolled by the cnvst and sclk digital inputs. cnvst controls the state of the t/h as well as when a conver- sion is initiated. cnvst also controls the power-down mode of the device (see the partial power-down (ppd) and full power-down (fpd) mode section). sclk clocks data out of the serial interface and sets the con- version speed. figures 4 and 5 show timing diagrams that outline the serial-interface operation. starting a conversion on power-up, the max1332/max1333 enter full power- down mode. the first rising edge of cnvst exits the full power-down mode and the max1332/max1333 begin acquiring the analog input. a cnvst falling edge initi- ates a conversion sequence. the t/h stage holds the input voltage; dout changes from high impedance to logic low; and the adc begins to convert at the first sclk rising edge. sclk is used to drive the conver- sion process, and it shifts data out of dout. sclk begins shifting out the data after the 4th rising edge of sclk. dout transitions t dot after each sclk? rising edge and remains valid for t dhold after the next rising edge. the 4th rising clock edge produces the msb of the conversion result at dout, and the msb remains valid t dhold after the 5th rising edge of sclk. sixteen max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs ______________________________________________________________________________________ 15 d11 0 0 0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dout sclk cnvst 0 power- mode selection window hold track analog input track and hold state 12345678910111213141516 t acq high-z t setup t conv continuous-conversion selection window figure 5. interface timing sequence cnvst sclk dout t setup t cfde t cp t crdd t dot t dhold t hold t csw figure 4. detailed serial-interface timing
max1332/max1333 rising sclk edges are needed to clock out the three leading zeros, 12 data bits, and a trailing zero. for con- tinuous operation, pull cnvst high between the 14th and the 15th rising edges of sclk. the highest throughput is achieved when performing continuous conversions. if cnvst is low during the rising edge of the 16th sclk, the dout line goes to a high-imped- ance state on either cnvst? rising edge or the next sclk? rising edge, enabling the serial interface to be shared by multiple devices. figure 6 illustrates a con- version using a typical serial interface. partial power-down (ppd) and full power- down (fpd) mode power consumption is reduced significantly by placing the max1332/max1333 in either partial power-down mode or full power-down mode. partial power-down mode is ideal for infrequent data sampling and fast wake-up time applications. once cnvst is transitioned from high to low, pull cnvst high any time after the 4th rising edge of the sclk but before the 13th rising edge of the sclk to enter partial power-down mode (see figure 7). drive cnvst low and then drive high before the 4th sclk to remain in partial power-down mode. this reduces the supply current to 3.3ma. drive cnvst low and allow at least 13 sclk cycles to elapse before dri- ving cnvst high to exit partial power-down mode. full power-down mode reduces the supply current to 0.2? and is ideal for infrequent data sampling. to enter full power-down mode, the max1332/max1333 must first be in partial power-down mode. while in par- tial power-down mode, repeat the sequence used to enter partial power-down mode to enter full power- down mode (see figure 8). drive cnvst low and allow at least 13 sclk cycles to elapse before driving cnvst high to exit full power-down mode. maintain a logic low or a logic high on sclk and all digital inputs at dv dd or dgnd while in either partial power-down or full power-down mode to minimize power consumption. 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 16 ______________________________________________________________________________________ d11 0 0 0 d10 d9 d8 d7 dout sclk cnvst dout goes high impedance once convst goes high convst must go high after 4th but before 13th sclk rising edge one 8-bit transfer 1st sclk rising edge normal ppd mode figure 7. spi interface?artial power-down 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 dout sclk cnvst 0 1 1 16 13 figure 6. continuous conversion with burst or continuous clock
another way of entering the full power-down mode is using the shdn input. drive shdn to a logic low to put the device into the full power-down mode. drive shdn high to exit full power-down mode and return to normal operating mode. shdn overrides any software-controlled power-down mode and every time it is deasserted, it places the max1332/max1333 in its normal mode of operation regardless of its previous state. transfer function the max1332/max1333 output is straight binary in unipolar mode and is two? complement in bipolar mode. figure 9 shows the unipolar transfer function for the max1332/max1333. table 1 shows the unipolar relation- ship between the differential analog input voltage and the digital output code. figure 10 shows the bipolar transfer function for the max1332/max1333. table 2 shows the bipolar relationship between the differential analog input voltage and the digital output code. max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs ______________________________________________________________________________________ 17 d11 0 0 0 d10 d9 d8 d7 dout sclk cnvst 0 000 0000 1st sclk rising edge 1st sclk rising edge normal mode execute partial power-down twice 1st 8-bit transfer 2nd 8-bit transfer ppd recovery fpd figure 8. spi interface?ull power-down zs = 0 fs = v ref 1 lsb = v ref 4096 fs fff ffe ffc ffb 000 001 003 004 output code (hex) differential input voltage (lsb) ffd 01234 fs - 1.5 lsb full-scale transition 002 figure 9. unipolar transfer function zs = 0 +fs = v ref 2 -fs = -v ref 2 1 lsb = v ref 4096 -fs +fs 7ff 7fe 001 000 800 801 ffe output code (hex) differential input voltage (lsb) fff 0 +fs - 1.5 lsb -fs + 0.5 lsb full-scale transition figure 10. bipolar transfer function
max1332/max1333 determine the differential analog input voltage as a function of v ref and the digital output code with the fol- lowing equation: where: code 10 = the decimal equivalent of the digital output code (see tables 1 and 2). ?.5 x lsb represents the quantization error that is inherent to any adc. when using a 4.096v reference, 1 lsb equals 1.0mv. when using a 2.5v reference, 1 lsb equals 0.61mv. applications information external reference the max1332/max1333 use an external reference between 1v and (av dd + 50mv). bypass ref with a 1? capacitor in parallel with a 0.1? capacitor to agnd for best performance (see the typical operating circuit ). connection to standard interfaces the max1332/max1333 serial interface is fully compat- ible with spi, qspi and microwire (see figure 11). if a serial interface is available, set the ?? serial inter- face in master mode so the ? generates the serial clock. choose a clock frequency based on the av dd and dv dd amplitudes. spi and microwire when using spi or microwire, the max1332/ max1333 are compatible with all four modes pro- grammed with the cpha and cpol bits in the spi or microwire control register. (this control register is in ? vv v lsb vv ain ain p ain n ref ref =? == __ 212 4096 ? v lsb code lsb ain = 10 05 . 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 18 ______________________________________________________________________________________ binary digital output code d11?0 hexadecimal equivalent of d11?0 decimal equivalent of d11?0 (code 10 ) differential input voltage (v) (v ref = 4.096v ) 1111 1111 1111 0xfff 4095 +4.095 ?.5 lsb 1111 1111 1110 0xffe 4094 +4.094 ?.5 lsb 1000 0000 0001 0x801 2049 +2.049 ?.5 lsb 1000 0000 0000 0x800 2048 +2.048 ?.5 lsb 0111 1111 1111 0x7ff 2047 +2.047 ?.5 lsb 0000 0000 0001 0x001 1 +0.001 ?.5 lsb 0000 0000 0000 0x000 0 +0.000 ?.5 lsb table 1. unipolar code table (max1332) two?-complement digital output code d11?0 hexadecimal equivalent of d11?0 decimal equivalent of d11?0 (code 10 ) differential input voltage (v) (v ref = 4.096v) 0111 1111 1111 0x7ff +2047 +2.047 ?.5 lsb 0111 1111 1110 0x7fe +2046 +2.046 ?.5 lsb 0000 0000 0001 0x001 +1 +0.001 ?.5 lsb 0000 0000 0000 0x000 0 0.000 ?.5 lsb 1111 1111 1111 0xfff -1 -0.001 ?.5 lsb 1000 0000 0001 0x801 -2047 -2.047 ?.5 lsb 1000 0000 0000 0x800 -2048 -2.048 ?.5 lsb table 2. bipolar code table (max1332)
the bus master, not the max1332/max1333.) conversion begins with a cnvst falling edge. dout goes low, indicating a conversion is in progress. two consecutive 1-byte reads are required to get the full 12 bits from the adc. dout transitions on sclk rising edges and is guaranteed to be valid t dot later and remain valid until t dhold after the following sclk rising edge. when using cpol = 0 and cpha = 0 or cpol = 1 and cpha = 1, the data is clocked into the ? on the following or next sclk rising edge. when using cpol = 0 and cpha = 1 or cpol = 1 and cpha = 0, the data is clocked into the ? on the next falling edge. see figure 11 for connections and figures 12 and 13 for timing. see the timing characteristics table to deter- mine the best mode to use. qspi unlike spi, which requires two 1-byte reads to acquire the 12 bits of data from the adc, qspi allows acquiring the conversion data with a single 16-bit transfer. the max1332/max1333 require 16 clock cycles from the ? to clock out the 12 bits of data. figure 14 shows a transfer using cpol = 1 and cpha = 1. the conver- sion result contains three zeros, followed by the 12 data bits and a trailing zero with the data in msb-first format. dsp interface to the tms320c54_ the max1332/max1333 can be directly connected to the tms320c54_ family of dsps from texas instruments. set the dsp to generate its own clocks or use external clock signals. use either the standard or buffered serial port. figure 15 shows the simplest inter- face between the max1332/max1333 and the tms320c54_, where the transmit serial clock (clkx) drives the receive serial clock (clkr) and sclk, and the transmit frame sync (fsx) drives the receive frame sync (fsr) and cnvst. for continuous conversion, set the serial port to trans- mit a clock and pulse the frame sync signal for a clock period before data transmission. use the serial port configuration (spc) register to set up with internal frame sync (txm = 1), clkx driven by an on-chip clock source (mcm = 1), burst mode (fsm = 1), and 16-bit word length (fo = 0). this setup allows continuous conversions provided that the data transmit register (dxr) and the data-receive register (drr) are serviced before the next conversion. alternately, autobuffering can be enabled when using the buffered serial port to execute conversions and read the data without ? intervention. connect dv dd to the tms320c54_ supply voltage. the word length can be set to 8 bits with fo = 1 to implement the power- down modes. the cnvst pin must idle high to remain in either power-down state. another method of connecting the max1332/max1333 to the tms320c54_ is to generate the clock signals external to either device. this connection is shown in figure 16 where serial clock (clock) drives the receive serial clock (clkr) and sclk, and the convert signal (convert) drives the receive frame sync (fsr) and cnvst. the serial port must be set up to accept an external receive clock and external receive frame sync. write the serial port configuration (spc) register as follows: txm = 0, external frame sync mcm = 0, clkx is taken from the clkx pin fsm = 1, burst mode fo = 0, data transmitted/received as 16-bit words this setup allows continuous conversion provided that the data-receive register (drr) is serviced before the next conversion. alternately, autobuffering can be max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs ______________________________________________________________________________________ 19 cnvst +3v to +5v sclk dout i/o sck miso a) spi ss max1332 max1333 cnvst sclk dout i/o sk si c) microwire max1332 max1333 cnvst +3v to +5v sclk dout cs sck miso b) qspi ss max1332 max1333 figure 11. common serial-interface connections to the max1332/max1333
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 20 ______________________________________________________________________________________ d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 dout high impedance high impedance sclk cnvst d0 16 12 figure 14. qspi serial-interface timing cnvst clkx dout sclk dv dd dv dd max1332 max1333 clkr tms320c54x fsx fsr dr figure 15. interfacing to the tms320c54_ internal clocks cnvst clkr dout sclk clock convert dv dd dv dd max1332 max1333 fsr tms320c54x dr figure 16. interfacing to the tms320c54_ external clocks d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 dout high impedance 1st byte read 2nd byte read high impedance sclk cnvst d0 16 189 figure 12. spi/microwire serial-interface timing?ingle conversion 0 0 0 d9d8d7d6d5d4d3d2d1d0 0 dout sclk cnvst 00 0 1 1 16 13 14 figure 13. spi/microwire serial-interface timing?ontinuous conversion
enabled when using the buffered serial port to read the data without ? intervention. connect dv dd to the tms320c54_ supply voltage. the max1332/max1333 can also be connected to the tms320c54_ by using the data transmit (dx) pin to drive cnvst and the transmit clock (clkx) generated internally to drive sclk. a pullup resistor is required on the cnvst signal to keep it high when dx goes high impedance and write (0001)h to the data transmit regis- ter (dxr) continuously for continuous conversions. the power-down modes can be entered by writing (00ff)h to the dxr (see figures 17 and 18). dsp interface to the adsp21_ _ _ the max1332/max1333 can be directly connected to the adsp21_ _ _ family of dsps from analog devices. figure 19 shows the direct connection of the max1332/max1333 to the adsp21_ _ _. there are two modes of operation that can be programmed to inter- face with the max1332/max1333. for continuous con- versions, idle cnvst low and pulse it high for one clock cycle during the lsb of the previous transmitted word. configure the adsp21_ _ _ stctl and srctl registers for early framing (lafr = 0) and for an active- high frame (ltfs = 0, lrfs = 0) signal. in this mode, the data-independent frame-sync bit (ditfs = 1) can be selected to eliminate the need for writing to the transmit data register more than once. for single con- versions, idle cnvst high and pulse it low for the entire conversion. configure the adsp21_ _ _ stctl and srctl registers for late framing (lafr = 1) and for an active-low frame (ltfs = 1, lrfs = 1) signal. this is also the best way to enter the power-down modes by setting the word length to 8 bits (slen = 0111). connect the dv dd pin to the adsp21_ _ _ supply volt- age (see figures 17 and 18). layout, grounding, and bypassing for best performance, use pc boards. wire-wrap boards must not be used. board layout must ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 20 shows the recommended system ground connections. establish an analog ground point at agnd and a digital ground point at dgnd. connect all other analog grounds to the analog ground point. max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs ______________________________________________________________________________________ 21 0 0 0 0 d11 d0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 dout sclk cnvst 00 d0 1 16 18 figure 17. dsp interface?ontinuous conversion 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 dout sclk cnvst 000 d0 1 1 figure 18. dsp interface?ingle conversion?ontinuous/burst clock
max1332/max1333 connect all digital grounds to the digital ground point. for lowest noise operation, make the power supply returns as low impedance and as short as possible. connect the analog ground point to the digital ground point together at the ic. high-frequency noise in the power supplies degrades the adc? performance. bypass av dd to agnd with 0.1? and 1? bypass capacitors. likewise, bypass dv dd to dgnd with 0.1? and 1? bypass capacitors. minimize capacitor lead lengths for best supply noise rejection. to reduce the effects of supply noise, a 10 ? resistor can be connected as a lowpass filter to attenu- ate supply noise (see figure 20). exposed paddle the max1332/max1333 tqfn package has an exposed paddle on the bottom of the package, providing a very low thermal resistance path for heat removal from the ic, as well as a low-inductance path to ground. the pad is electrically connected to agnd on the max1332/ max1333 and must be soldered to the circuit board ana- log ground plane for proper thermal and electrical perfor- mance. refer to the maxim application note hfan-08.1: thermal considerations for qfn and other exposed pad packages , for additional information. definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. for the max1332/ max1333, this straight line is between the end points of the transfer function once offset and gain errors have been nullified. inl deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics table. differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. for the max1332/ max1333, dnl deviations are measured at every step and the worst-case deviation is reported in the electri- cal characteristics table. offset error offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. typically, the point at which the offset error is specified is at or near the zero-scale of the transfer function or at or near the midscale of the transfer function. for the max1332/max1333, operating with a unipolar transfer function, the ideal zero-scale digital output transition from 0x000 to 0x001 occurs at 0.5 lsb above agnd. unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point. for the max1332/max1333, operating with a bipolar transfer function, the ideal midscale digital output tran- sition from 0xfff to 0x000 occurs at 0.5 lsb below agnd. bipolar offset error is the amount of deviation 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 22 ______________________________________________________________________________________ cnvst tclk dout sclk dv dd vddint max1332 max1333 rclk adsp21_ _ _ tfs rfs dr figure 19. interfacing to the adsp21_ _ _ analog supply av dd agnd dv dd data dgnd digital circuitry av dd return digital ground point digital supply return dv dd dgnd dv dd max1332 max1333 analog ground point *optional 10 ? * figure 20. power-supply grounding condition
between the measured midscale transition point and the ideal midscale transition point. gain error gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. for the max1332/ max1333, the gain error is the difference of the mea- sured full-scale and zero-scale transition points minus the difference of the ideal full-scale and zero-scale transition points. for the unipolar input, the full-scale transition point is from 0xffe to 0xfff and the zero-scale transition point if from 0x000 to 0x001. for the bipolar input, the full-scale transition point is from 0x7fe to 0x7ff and the zero-scale transition point is from 0x800 to 0x801. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling edge of the cnvst and the instant when an actual sample is taken (figure 21). signal-to-noise ratio (snr) snr is a dynamic figure of merit that indicates the con- verter? noise performance. for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade snr. for the max1332/max1333, snr is computed by tak- ing the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is a dynamic figure of merit that indicates the converter? noise and distortion performance. sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset: effective number of bits (enob) enob specifies the global accuracy of an adc at a spe- cific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full- scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is a dynamic figure of merit that indicates how much harmonic distortion the converter adds to the signal. thd is the ratio of the rms sum of the first five harmon- ics of the fundamental signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 6 are the amplitudes of the 2nd- through 6th-order harmonics. thd vvvvv v = ++++ ? ? ? ? ? ? ? ? 20 23456 1 22222 log enob sinad = ? 176 602 . . sinad db signal noise distortion rms rms ( ) log () = + ? ? ? ? ? ? 20 max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs ______________________________________________________________________________________ 23 hold analog input sampled data (t/h) t/h t ad t aj track track cnvst figure 21. t/h aperture timing
max1332/max1333 spurious-free dynamic range (sfdr) sfdr is a dynamic figure of merit that indicates the lowest usable input signal amplitude. sfdr is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest spurious component, excluding dc offset. sfdr is specified in decibels relative to the carrier (dbc). intermodulation distortion (imd) imd is the total power of the im2 to im5 intermodulation products to the nyquist frequency relative to the total input power of the two input tones f in1 and f in2 . the individual input tone levels are at -7dbfs. the inter- modulation products are as follows: 2nd-order intermodulation products (im2): f in1 + f in2 , f in2 - f in1 3rd-order intermodulation products (im3): 2f in1 - f in2 , 2f in2 - f in1 , 2f in1 + f in2 , 2f in2 + f in1 4th-order intermodulation products (im4): 3f in1 - f in2 , 3f in2 - f in1 , 3f in1 + f in2 , 3f in2 + f in1 5th-order intermodulation products (im5): 3f in1 - 2f in2 , 3f in2 - 2f in1 , 3f in1 + 2f in2 , 3f in2 + 2f in1 channel-to-channel isolation channel-to-channel isolation is a figure of merit that indicates how well each analog input is isolated from the others. the channel-to-channel isolation for the max1332/max1333 is measured by applying a low-fre- quency 500khz -0.5dbfs sine wave to the on channel while a high-frequency 900khz -0.5dbfs sine wave is applied to the off channel. an fft is taken for the on channel. from the fft data, channel-to-channel crosstalk is expressed in db as the power ratio of the 500khz low-frequency signal applied to the on channel and the 900khz high-frequency crosstalk signal from the off channel. full-power bandwidth a large -0.5db fs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. full-linear bandwidth full-linear bandwidth is the frequency at which the sig- nal-to-noise plus distortion (sinad) is equal to 68db. the amplitude of the analog input signal is -0.5dbfs. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in such a way that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. power-supply rejection (psr) psr is defined as the shift in offset error when the ana- log power supply is moved from 2.7v to 3.6v. 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs 24 ______________________________________________________________________________________ 16 1 2 3 4 12 11 10 9 15 14 13 5 6 7 8 agnd av dd dgnd dv dd dout sclk cnvst chsel ain0n ain1p ain1n ref shdn bip/uni agnd ain0p top view max1332 max1333 pin configuration chip information process: bicmos part av dd (v) max sampling rate (msps) max1332ete +5 3 MAX1333ETE +3 2 selector guide
max1332/max1333 3msps/2msps, 5v/3v, 2-channel, true- differential 12-bit adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 12x16l qfn thin.eps 0.10 c 0.08 c 0.10 m c a b d d/2 e/2 e a1 a2 a e2 e2/2 l k e (nd - 1) x e (ne - 1) x e d2 d2/2 b l e l c l e c l l c l c e 1 2 21-0136 package outline 12, 16l, thin qfn, 3x3x0.8mm 1. dimensioning & tolerancing conform to asme y14.5m-1994. exposed pad variations 1.10 t1633-1 0.95 codes pkg. t1233-1 min. 0.95 nom. 1.10 d2 1.25 1.10 0.95 1.25 nom. 1.10 max. 1.25 min. 0.95 max. 1.25 e2 12 n k a2 0.25 ne a1 nd 0 0.20 ref - - 3 0.02 3 0.05 l e e 0.45 2.90 b d a 0.20 2.90 0.70 0.50 bsc. 0.55 3.00 0.65 3.10 0.25 3.00 0.75 0.30 3.10 0.80 16 0.20 ref 0.25 - 0 4 0.02 4 - 0.05 0.50 bsc. 0.30 2.90 0.40 3.00 0.20 2.90 0.70 0.25 3.00 0.75 3.10 0.50 0.80 3.10 0.30 pkg ref. min. 12l 3x3 nom. max. nom. 16l 3x3 min. max. 0.35 x 45 pin id jedec weed-1 0.35 x 45 weed-2 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220 revision c. notes: e 2 2 21-0136 package outline 12, 16l, thin qfn, 3x3x0.8mm t1233-3 1.10 1.25 0.95 1.10 0.35 x 45 1.25 weed-1 0.95 t1633f-3 0.65 t1633-4 0.95 0.80 0.95 0.65 0.80 1.10 1.25 0.95 1.10 0.225 x 45 0.95 weed-2 0.35 x 45 1.25 weed-2 t1633-2 0.95 1.10 1.25 0.95 1.10 0.35 x 45 1.25 weed-2 no down bonds allowed yes no yes n/a no

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